1. Field of the Invention
The present invention relates to the field of computer systems, and more particularly, to a multiprocessor computer system coupled to devices external to the multiprocessor computer system via an input/output bridge.
2. Description of the Relevant Art
Personal computers (PCs) and other types of computer systems have been designed around a shared bus system for accessing memory. One or more processors and one or more input/output (I/O) devices may be coupled to the memory through the shared bus. The I/O devices may be coupled to the shared bus through an I/O bridge which manages the transfer of information between the shared bus and the I/O devices, while processors are typically coupled directly to the shared bus or coupled through a cache hierarchy to the shared bus.
Unfortunately, shared bus systems suffer from several drawbacks. For example, since there are multiple devices attached to the shared bus, the bus is typically operated at a relatively low frequency. The multiple attachments present a high capacitive load to a device driving a signal on the bus, and the multiple attach points present a relatively complicated transmission line model for high frequencies. Accordingly, the frequency remains low, and the bandwidth available of the shared bus is similarly relatively low. A low bandwidth presents a barrier to attaching additional devices to the shared bus, as performance may be limited by available bandwidth.
Another disadvantage of the shared bus system is a lack of scalability to larger numbers of devices. As mentioned above, the amount of bandwidth is fixed and may decrease if additional devices are added. Once the bandwidth requirements of the devices attached to the bus, either directly or indirectly, exceeds the available bandwidth of the bus, devices will frequently be stalled when attempting to access the bus. As a result, overall performance may be decreased.
One or more of the above problems may be addressed using a distributed memory system. A computer system employing a distributed memory system includes multiple nodes. Two or more of these nodes are connected to individual memories, respectively, and the nodes are interconnected using any suitable interconnect. For example, each node may be connected to each other node using dedicated lines. Alternatively, each node may connect to a fixed number of other nodes, and transactions between nodes may be routed from a first node to a second node to which the first node is not directly connected via one or more intervening nodes. A memory address space is assigned across the memories in each node.
Nodes may additionally include a processor. The processor typically includes a cache which stores cache blocks of data read from the memories. Furthermore, a node may include one or more caches external to the processors. Since the processors and/or nodes may be storing cache blocks accessed by other nodes, it is desirable to maintain coherency within the nodes.
The present invention provides a method and circuit for selectively stalling interrupt requests initiating from one or more devices coupled to a multiprocessor system via an I/O bridge. In one embodiment, the multiprocessor system includes a plurality of circuit nodes and a plurality of memories. Each circuit node may include at last one microprocessor coupled to a memory controller which, in turn, is coupled to one of the memories. The plurality of circuit nodes are in data communication with each other so that one circuit node may communicate with another circuit node directly or indirectly through one or more intermediate circuit nodes.
A first circuit node is coupled to an I/O bridge to affect data communication there between. Other circuit nodes may likewise be coupled to separate I/O bridges. The first I/O bridge, in turn, may be coupled to one or more I/O buses or devices such as graphic devices. The I/O buses, in turn, may be coupled to one or more I/O devices or a secondary bus bridge.
In one embodiment of the present invention, the I/O bridge generates a non-coherent memory access command packet. This non-coherent memory access command packet comprises a first pipe identification. Pipe identifications are used to identify, for example, one or more I/O devices coupled to the I/O bridge via an I/O bus. The I/O bridge generates the non-coherent memory access command packet in response to a memory access request originating with one of the I/O devices coupled directly or indirectly to the I/O bridge. The I/O bridge transmits the non-coherent memory access command packet to the first circuit node via a non-coherent link connected between the I/O bridge and the first circuit node. The first circuit node receives the non-coherent memory access command packet and generates a coherent memory access command packet using information in the received non-coherent memory access command packet, such as, for example, a memory address where data is to be written or read. The first circuit node then transmits the non-coherent memory access command packet to a second circuit node within the multiprocessor system.
Subsequent to generating the non-coherent memory access command packet, the I/O bridge generates a non-coherent interrupt command packet. The I/O bridge generates the non-coherent interrupt command packet in response to, for example, an interrupt request generated by an I/O device coupled directly or indirectly to the I/O bridge. This non-coherent interrupt command packet includes a second pipe identification which may or may not equate to the first pipe identification of the non-coherent memory access command packet. The first circuit node receives the non-coherent interrupt command packet and, in response, generates a coherent interrupt command packet using information contained within the received non-coherent interrupt command packet. While the coherent interrupt command packet will be transmitted to another circuit node, the transmission may be delayed. More particularly, after the first circuit node receives the non-coherent interrupt command packet, the first circuit node compares the first and second pipe identifications contained within the non-coherent memory access command packet and non-coherent interrupt command packet, respectively. If the first and second pipe identifications compare unequally, then the first circuit transmits the coherent interrupt command packet to another circuit node without the above-mentioned delay. If, however, the first and second pipe identifications compare equally, the first circuit node may delay transmission of a coherent interrupt command packet.